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| K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E Document Title 1Mx4 Bit High Speed Static RAM(5V Operating). Operated at Extended and Industrial Temperature Ranges. PRELIMINARY CMOS SRAM Revision History Rev No. Rev. 0.0 Rev. 1.0 History Initial release with Preliminary. 1.1 Removed Low power Version. 1.2 Removed Data Retention Characteristics 1.3 Changed ISB1 to 20mA 2.1 Relax D.C parameters. Item ICC 12ns 15ns 20ns Previous 160mA 155mA 150mA Current 190mA 185mA 180mA Draft Data Feb. 12. 1999 Mar. 29. 1999 Remark Preliminary Preliminary Rev. 2.0 Aug. 19. 1999 Preliminary 2.2 Relax Absolute Maximum Rating. Item Voltage on Any Pin Relative to Vss Rev. 3.0 3.1 Delete Preliminary 3.2 Update D.C parameters and 10ns part. ICC 190mA 185mA 180mA Previous Isb 70mA Isb1 20mA ICC 160mA 150mA 140mA 130mA Current Isb 60mA Isb1 10mA Previous -0.5 to 7.0 Current -0.5 to Vcc+0.5 Mar. 27. 2000 Final 10ns 12ns 15ns 20ns 3.3 Added Extended temperature range The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Rev 3.0 March 2000 K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E 1M x 4 Bit (with OE)High-Speed CMOS Static RAM FEATURES * Fast Access Time 10,12,15,20ns(Max.) * Low Power Dissipation Standby (TTL) : 60mA(Max.) (CMOS) : 10mA(Max.) Operating K6R4004C1C-10 : 160mA(Max.) K6R4004C1C-12 : 150mA(Max.) K6R4004C1C-15 : 140mA(Max.) K6R4004C1C-20 : 130mA(Max.) * Single 5.0V 10% Power Supply * TTL Compatible Inputs and Outputs * I/O Compatible with 3.3V Device * Fully Static Operation - No Clock or Refresh required * Three State Outputs * Center Power/Ground Pin Configuration * Standard Pin Configuration K6R4004C1C-J : 32-SOJ-400 PRELIMINARY CMOS SRAM GENERAL DESCRIPTION The K6R4004C1C is a 4,194,304-bit high-speed Static Random Access Memory organized as 1,048,576 words by 4 bits. The K6R4004C1C uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNGs advanced CMOS process and designed for highspeed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R4004C1C is packaged in a 400 mil 32-pin plastic SOJ. PIN CONFIGURATION(Top View) A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 A19 A18 A17 A16 A15 OE ORDERING INFORMATION K6R4004C1C-C10/C12/C15/C20 K6R4004C1C-E10/E12/E15/E20 K6R4004C1C-I10/I12/I15/I20 Commercial Temp. Extended Temp. Industrial Temp. A1 A2 A3 A4 CS I/O1 26 I/O4 FUNCTIONAL BLOCK DIAGRAM Clk Gen. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 I/O1~I/O4 Vcc Vss I/O2 SOJ 25 24 Vss Vcc 23 I/O3 22 21 20 19 18 A14 A13 A12 A11 A10 Pre-Charge Circuit WE A5 A6 Row Select A7 Memory Array 1024 Rows 1024 x 4 Columns A8 A9 17 N.C Data Cont. CLK Gen. I/O Circuit Column Select PIN FUNCTION Pin Name A0 - A19 WE Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+5.0V) Ground No Connection A10 A12 A14 A16 A18 A11 A13 A15 A17 A19 CS OE I/O1 ~ I/O4 CS WE OE VCC VSS N.C -2- Rev 3.0 March 2000 K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Commercial Extended Industrial Symbol VIN, VOUT VCC PD TSTG TA TA TA Rating -0.5 to VCC+0.5 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -25 to 85 -40 to 85 PRELIMINARY CMOS SRAM Unit V V W C C C C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5** Typ 5.0 0 Max 5.5 0 VCC+0.5*** 0.8 Unit V V V V * The above parameters are also guaranteed at extended and industrial temperature range. ** VIL(Min) = -2.0V a.c(Pulse Width 8ns) for I 20mA. *** VIH(Max) = VCC + 2.0V a.c (Pulse Width 8ns) for I 20mA. DC AND OPERATING CHARACTERISTICS*(TA=0 to 70C, Vcc=5.0V10%, unless otherwise specified) Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC VIN=VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA Com. 10ns 12ns 15ns 20ns Ext. Ind. 10ns 12ns 15ns 20ns Standby Current ISB ISB1 Output Low Voltage Level Output High Voltage Level VOL VOH VOH1** Min. Cycle, CS=VIH f=0MHz, CSVCC-0.2V, VINVCC-0.2V or VIN0.2V IOL=8mA IOH=-4mA IOH1=-0.1mA Test Conditions Min -2 -2 2.4 Max 2 2 160 150 140 130 175 165 155 145 60 10 0.4 3.95 V V V mA Unit A A mA * The above parameters are also guaranteed at extended and industrial temperature range. ** VCC=5.0V5%, Temp.=25C. CAPACITANCE*(TA=25C, f=1.0MHz) Item Input/Output Capacitance Input Capacitance * Capacitance is sampled and not 100% tested. Symbol CI/O CIN Test Conditions VI/O=0V VIN=0V MIN - Max 8 7 Unit pF pF -3- Rev 3.0 March 2000 K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E AC CHARACTERISTICS(TA=0 to 70C, VCC=5.0V10%, unless otherwise noted.) TEST CONDITIONS* Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads * The above test conditions are also applied at extended and industrial temperature range. PRELIMINARY CMOS SRAM Value 0V to 3V 3ns 1.5V See below Output Loads(A) Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5.0V RL = 50 DOUT VL = 1.5V ZO = 50 30pF* 480 DOUT 255 5pF* * Capacitive Load consists of all components of the test environment. * Including Scope and Jig Capacitance READ CYCLE* Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Chip Selection to Power Up Time Chip Selection to Power DownTime Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tPU tPD K6R4004C1C-10 K6R4004C1C-12 K6R4004C1C-15 K6R4004C1C-20 Min 10 3 0 0 0 3 0 - Max 10 10 5 5 5 10 Min 12 3 0 0 0 3 0 - Max 12 12 6 6 6 12 Min 15 3 0 0 0 3 0 - Max 15 15 7 7 7 15 Min 20 3 0 0 0 3 0 - Max 20 20 8 9 9 20 Unit ns ns ns ns ns ns ns ns ns ns ns * The above parameters are also guaranteed at extended and industrial temperature range. -4- Rev 3.0 March 2000 K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E WRITE CYCLE* Parameter Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWP1 tWR tWHZ tDW tDH tOW K6R4004C1C-10 K6R4004C1C-12 K6R4004C1C-15 PRELIMINARY CMOS SRAM K6R4004C1C-20 Min 10 7 0 7 7 10 0 0 5 0 3 Max 5 - Min 12 8 0 8 8 12 0 0 6 0 3 Max 6 - Min 15 10 0 10 10 15 0 0 7 0 3 Max 7 - Min 20 12 0 12 12 20 0 0 9 0 3 Max 9 - Unit ns ns ns ns ns ns ns ns ns ns ns * The above parameters are also guaranteed at extended and industrial temperature range. TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tOH Data Out Previous Valid Data tAA Valid Data TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO tOE OE tOLZ tLZ(4,5) Valid Data ICC ISB tPU 50% tPD 50% tOH tHZ(3,4,5) CS tOHZ Data out VCC Current NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. -5- Rev 3.0 March 2000 K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tAW OE tCW(3) CS tAS(4) WE tDW Data in High-Z tOHZ(6) Data out High-Z(8) Valid Data tWP(2) PRELIMINARY CMOS SRAM tWR(5) tDH TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in High-Z tWHZ(6) Data out High-Z(8) Valid Data tOW (10) (9) tWR(5) tWP1(2) tDH TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled) tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in tDH tWP(2) tWR(5) High-Z tLZ tWHZ(6) Valid Data High-Z Data out High-Z High-Z(8) -6- Rev 3.0 March 2000 K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E NOTES(WRITE CYCLE) PRELIMINARY CMOS SRAM 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION CS H L L L * X means Dont Care. WE X H H L OE X* H L X Mode Not Select Output Disable Read Write I/O Pin High-Z High-Z DOUT DIN Supply Current ISB, ISB1 ICC ICC ICC -7- Rev 3.0 March 2000 K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E PACKAGE DIMENSIONS PRELIMINARY CMOS SRAM Units:millimeters/Inches 32-SOJ-400 #32 #17 10.16 0.400 11.18 0.12 0.440 0.005 9.40 0.25 0.370 0.010 0.20 #1 21.36 MAX 0.841 20.95 0.12 0.825 0.005 ( 1.30 ) 0.051 ( 1.30 ) 0.051 0.43 +0.10 -0.05 +0.10 -0.05 #16 0.69 0.027 MIN 0.008 +0.004 -0.002 3.76 MAX 0.148 0.10 MAX 0.004 ( 0.95 ) 0.0375 0.017+0.004 -0.002 1.27 0.050 0.71 +0.10 -0.05 0.028 +0.004 -0.002 -8- Rev 3.0 March 2000 |
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